The present disclosure relates to processing systems and, more particularly, to an integrated wafer-level processing system.
Server and cloud computing solutions need low cost memory with higher bandwidth and much lower latency for improved performance. Current packaging solutions can be used but have limitations on bandwidth, latency and cost.
Current implementations may use a board trace to connect a processor to memory cards (i.e., a multiplicity of dual in-line memory modules (DIMMs)). Current implementations using a board (e.g., a motherboard) to connect a processor to memory cards use longer communicative paths that result in slower data transfer between the processor and the memory. Moreover, current implementations utilize course pin connects that limit the number of connections between the processor and the memory cards. Additionally, the inclusion of the board, associated packaging, and interconnections to connect the processor to the memory increases cost.
In current implementations, each DIMM contains groups of dynamic random-access memory (DRAM) chips (e.g., 8 DRAM chips per DIMM, 16 DRAM chips per DIMM, etc.) referred to as a rank. A rank of DRAM chips responds together to a memory command (e.g., a read command, a write command, etc.), and, in a processing system, a rank may include extra DRAM chips on each DIMM (e.g., 1-2 spares) for backup purposes. Error checking and correcting codes enable one of these DRAM chips in a rank to become partially or completely bad, and the processing system is still able to function with correct data.